Active-matrix display devices require a scan signal line driving circuit and data signal line driving circuit for driving an array of pixels disposed in a matrix. The scan signal line driving circuit and data signal line driving circuit use shift registers to drive the gate lines and source lines in predetermined sequence. The shift register is realized by multiple stages of flip-flops connected to one another.
The following will describe a structure of conventional flip-flops making up a shift register. The flop-flop described below is a set-reset flip-flop (hereinafter “RS flip-flop”) having a control terminal GB, an input terminal CK, a reset terminal RB, and an output terminal OUT, as illustrated in FIG. 17.
FIG. 18 shows an exemplary structure of the RS flip-flop. The RS flip-flop shown in FIG. 18 includes an inverter circuit 101 in which a p-type transistor Mp1 and an n-type transistor Mn1 (hereinafter, p-type transistors and n-type transistors will be denoted by Mp and Mn, respectively) are connected in series between power supply VDD (high potential) and VSS (low potential). A control terminal GB is connected to the input side of the inverter circuit 101, i.e., to the gates of the Mp1 and Mn1.
Between the power supply VDD and the input terminal CK are serially connected a CMOS analog switch ASW and Mp3, wherein the CMOS analog switch ASW includes Mn2 and Mp2 connected parallel to each other. In the analog switch ASW, the gate of Mn2 is connected to the output of the inverter circuit 101 (junction between the source of Mp1 and the drain of Mn1), and the gate of Mp2 is connected to the control terminal GB. The gate of Mp3 is connected to a reset terminal RB.
Supplying VDD to the gate of Mn2 in the analog switch ASW connects the source and drain of Mn2, while the source and drain of Mn2 is cut off when VSS is supplied. On the other hand, supplying VSS to the gate of Mp2 connects the source and drain of Mp2, while the source and drain of Mp2 is cut off when the gate of Mp2 is connected to VDD. By these operations of Mn2 and Mp2, the analog switch ASW controls the supply of input signal CK.
Between power supply VDD and VSS, the RS flip-flop includes an inverter circuit 102 including Mp4 and Mn4, and an inverter circuit 103 including Mp5 and Mn5. The inverter circuit 102 and the inverter circuit 103 together form a latch circuit by connecting their inputs and outputs to each other (an input of the inverter circuit 102 is connected to an output of the inverter circuit 103, and an output of the inverter circuit 102 is connected to an input of the inverter circuit 103). Between the Mn4 of the inverter circuit 102 and the power supply VSS is an Mn6, whose gate is connected to the reset terminal RB.
The junction between Mp3 and the analog switch ASW is connected to an output of the inverter circuit 102 (the junction between the source of Mp4 and the drain of Mn4). (The junction of Mp3 and the analog switch ASW, and the output of the inverter circuit 102 have a Node A potential.) An output of the inverter circuit 103 (the junction between the source of Mp5 and the drain of Mn5) is connected to the output terminal OUT.
In the RS flip-flop, the inverter circuit 101, Mp3, and analog switch ASW realize a gating section. The inverter circuit 102, inverter circuit 103, and Mn6 realize a latch section. The gating section is a functional block for sending an externally supplied input signal to the latch section of the following stage according to a control signal separately supplied from the input signal. The latch section is a functional block for latching the input signal supplied from the gating section.
Referring to FIG. 19, the following will describe operations of the RS flip-flop shown in FIG. 18.
A timing chart of FIG. 19 assumes that the control signal GB, clock signal CK, and reset signal RB are respectively input to the control terminal GB, input terminal CK, and reset terminal RB of the RS flip-flop.
First, when the control signal GB falls to low (VSS) at time t1, the output of the inverter circuit 101 becomes VDD, and the VDD is supplied to the gate of Mn2 in the analog switch ASW. Here, the gate of Mp2 in the analog switch ASW receives VSS (control signal GB).
As a result, the analog switch ASW closes, supplying the input signal CK to the Node A. Here, the reset signal RB is high (VDD) and the Mp3 is open. Accordingly, the Node A has the potential of the input signal CK.
The high level (VDD) reset signal RB is also supplied to the gate of Mn6. With the Mn6 turned on, the MN4 and Mp4 can operate as the inverter circuit 102. The potential of the Node A is the input of the inverter circuit 103. Accordingly, in this state, the output of the inverter circuit 103—the output signal OUT of the RS flip-flop—is low (VSS). When the potential at the junction between the input of the inverter circuit 102 and the output of the output circuit 103 is regarded as a Node B potential, the Node B potential is also at low level. Here, the potential of the output signal OUT is latched by the inverter circuit 102 and the inverter circuit 103.
When the clock signal CK becomes low (VSS) at time t2, the potential of the Node A becomes (VSS) low. The Node B potential and the output signal OUT become high (VDD).
When the control signal GB becomes high (VDD) at time t3, the analog switch ASW1 opens, stopping supply of the clock signal CK to the Node A. Here, since the reset signal RB remains high (VDD), the Mn6 is ON and the inverter circuits 102 and 103 operate as a latch circuit. Accordingly, the Node A potential remains low (VSS), and the Node B potential and the output signal (OUT) remain high (VDD).
When the reset signal RB becomes low (VSS) at time t4, the Mp3 is turned on and the Mn6 is turned off. Accordingly, the Mn4 and Mp4 do not operate as the inverter circuit 102, canceling the latch state. With the Mp3 turned on, the Node A potential becomes high (VDD), which is supplied to the respective gates of the Mn5 and Mp5 making up the inverter circuit 103. As a result, the Node B potential and the output signal OUT become low (VSS).
After time t5, the control signal GB is high (VDD), and the signal CK is not applied to the Node A. Further, since the reset signal RB is high, the Mp3 is turned off, and the Mn6 is turned on. This operates the inverter circuit 102 and causes it to latch the Node B potential and the output signal OUT with the latch circuit 103. The Node B potential and the output signal OUT are maintained at low level (VSS).
Referring to FIG. 20, the following will describe another exemplary structure of the RS flip-flop.
An RS flip-flop shown in FIG. 20 is structured such that it receives a control signal GB, a clock signal CK, an inverted clock signal CKB, and a reset signal RB, wherein the clock signal CK and inverted clock signal CKB have amplitudes smaller than that produced by VDD, which is a power supply of the flip-flop.
As with the RS flip-flop of FIG. 18, the RS flip-flop shown in FIG. 20 includes a gating section and a latch section. The latch section is the same as that in the RS flip-flop of FIG. 18. Only the gating section is different.
In the gating section of the RS flip-flop shown in FIG. 20, Mp11 and Mn11 are connected in series between the power supply VDD and the input terminal CKB, and Mp12 and Mn12 are connected in series between the power supply VDD and the input terminal CK. An Mn13 is disposed between a power supply VSS and the junction of the Mp11 source and Mn11 drain.
The respective gates of the Mp11 and Mn13 are connected to the control terminal GB. The respective gates of the Mn11 and Mn12 are connected to the junction between the Mp11 source and Mn11 drain. The gate of the Mp12 is connected to the reset terminal RB. The junction between the Mp12 source and Mn12 drain is connected to Node A. The junction between the Mp11 source and Mn11 drain is Node C.
In the RS flip-flop structured as shown in FIG. 20, it is assumed, for example, that the clock signal and inverted clock signal CKB each have an amplitude of 3.3 V, and that the VDD and VSS of the circuit are 8 V and 0 V, respectively. For example, when the GB terminal is low and the threshold of the n-type transistors in the circuit is 3.5 V, supplying a low level signal CKB (VSS=0 V) and a 3.3 V signal CK turns on Mp11 and causes Mn11 to operate in a diode-like manner. As such, the Node C maintains a potential near 3.5 V, close to the threshold of Mn11.
Here, the clock signal CK is supplied to the source of Mn12, and the gate of the Mn12 is connected to Node C. Accordingly, the gate-source potential of the Mn12 is about 0.2 V. Here, the Mn12 is turned off when it has a threshold of about 3.5 V as does the Mn11.
On the other hand, when the inverted clock signal CKB and clock signal CK are 3.3 V and 0 V, respectively, the Node C has a potential of about 6.8 V by adding the 3.5 V threshold of Mn11 to 3.3 V. Here, since the clock signal CK is 0 V, the source-gate voltage of Mn12 is about 6.8 V even when the threshold of Mn12 is 3.5 V. Accordingly, the Mn12 is turned on, and the Node A is 0 V.
Referring to FIG. 21, the following will describe operations of the RS flip-flop shown in FIG. 20.
A timing chart shown in FIG. 21 assumes that the control signal GB, clock signal CK, inverted clock signal CKB, and reset signal RB are respectively input to the control terminal GB, input terminal CK, input terminal CKB, and reset terminal RB of the RS flip-flop.
When the control signal GB becomes low (VSS) at time t1, the Mp11 is turned on and Mn13 is turned off. Here, since the inverted clock signal CKB, the clock signal CK, and the threshold voltage of Mn11 are 0V, 3.3 V, and 3.5 V, respectively, the gate potential of Mn12 (Node C potential) is about 3.5 V, and the source potential of Mn12 is 3.3 V. As such, the Mn12 is turned off. Here, since the reset signal RB is high (VDD=8 V), the Mp12 is off and Mn6 is on, causing the Mp4 and Mn4 to operate as the inverter circuit 102. The inverter circuit 102 forms a latch circuit with the inverter circuit 103 including Mp5 and Mn5, and accordingly the Node A remains at low level.
At time t2, when the inverted clock signal CKB and clock signal CK become 3.3 V and 0 V, respectively, the node C becomes about 6.8 V by adding 3.3 V to the 3.5 V threshold of the Mn11. The potential of the node C is applied to the gate of Mn12. Here, since the source of Mn12 is 0 V, the Mn12 is turned on and the Node A becomes low. Here, the reset signal RB is still at high level (VDD=8 V), the Mp12 is off and Mn6 is on, causing the Mp4 and Mn4 to operate as the inverter circuit 102. When the Node A becomes low, the latch circuit realized by the inverter circuits 102 and 103 changes its state, and the output signal OUT becomes high (VDD=8 V).
At time t3, the control signal GB becomes high (VDD=8 V), turning off the Mp11, and turning on the Mn13. As a result, the respective gates of the Mn11 and Mn12 become low level (VSS=0 V), cutting off the clock signal CK and inverted clock signal CKB. Thus, when the control signal GB is at high level (VDD=8 V), the flip-flop will not be affected by the clock signal CK or inverted clock signal CKB regardless of the states of these clock signals. Here, since the Mn12 is off, no clock signal CK is supplied to the Node A. The Node A is maintained at low level by the latch circuit realized by the inverter circuits 102 and 103, and the output OUT remains at high level (VDD=8 V).
After time t4, the reset signal RB becomes low (VSS=0 V), and the Mp12 is turned on. At the same time, the reset signal RB is also supplied to the gate of Mn6, turning on the Mn6. Accordingly, the Mn4 and Mp4 do not operate as the inverter circuit 102. As a result, the Node A becomes high (VDD=8 V), and the output signal OUT becomes low as it passes through the inverter circuit 103.
At time t5, the reset signal RB becomes high, turning off the Mp12, and turning on the Mn6. This causes the circuit including Mn4 and Mp4 to operate as the inverter circuit 102 again, causing the inverter circuit 102 to operate as a latch circuit again with the inverter circuit 103. As a result, the Node A is maintained at high level, and accordingly the output signal OUT is maintained at low level.
FIG. 22 illustrates an exemplary structure of a shift register using RS flip-flops structured as above. The shift register shown in FIG. 22 uses the RS flip-flop shown in FIG. 18.
The shift register includes a plurality of serially connected RS flip-flops FF1, FF2, . . . , wherein an input terminal CK of an RS flip-flop FFa (a=2n−1, n=1, 2, . . . ) receives a clock signal CK, and an input terminal CK of an RS flip-flop FFa (a=2n, n=1, 2, . . . ) receives an inverted clock signal CKB.
A GB terminal of a first-stage RS flip-flop FF1 receives a start pulse signal SPB, and an output OUT from each stage of RS flip-flops FFa becomes the output (Q1, Q2, Q3, . . . ) of the shift register. Further, an output Q1 from each stage of the RS flip-flops FF1, FF2, . . . is supplied (GB2, GB3, . . . ) through an inverter to a GB terminal of the next-stage RS flip-flop FF.
In the RS flip-flops FF2, FF3, . . . of the second and subsequent stages, an inverted signal of the output (Q2, Q3, . . . ) is supplied to a GB terminal of the next stage, and also to an RB terminal of the RS flip-flop of the preceding stage, where the output is used as a reset signal. For example, a signal GB3, which is an inverted signal of the output Q2 of the second-stage RS flip-flop FF2, is supplied to the GB terminal of the third-stage RS flip-flop FF3, and to the RB terminal of the first-stage RS flip-flop FF1.
Referring to a timing chart of FIG. 23, the following will describe operations of the shift register.
At time t1, a start pulse signal SPB is supplied to the GB terminal of FF1. When the clock signal becomes low at time t2, the OUT signal of the FF1, i.e., signal Q1, becomes high. The signal Q1 is supplied as a signal GB2 to the GB terminal of FF2 via the inverter. That is, the GB terminal of the FF2 receives a low level signal.
With the signal GB2 of a low level supplied to the GB terminal of FF2, changing the inverted clock signal CKB to low at time t3 causes the OUT signal of FF2, i.e., signal Q2, to be a high level. The signal GB3, which is the inverted signal of the signal Q2, becomes low. The signal GB3 is supplied to the GB terminal of FF3. The signal GB3 is also supplied to the RB terminal of FF1, resetting FF1 and switching Q1 to low.
In this manner, the serially connected set-reset flip-flops serve as a shift register in synchronism with signal CK and signal CKB. The shift register is operative even when the signal CK and signal CKB have smaller amplitudes than the power voltage VDD of the circuit.
Meanwhile, Japanese Laid-Open Patent Publication No. 356728/2001 (published on Dec. 26, 2001; corresponding U.S. Pat. No. 6,377,104B2) discloses a static clock pulse generator including multiple stages of D-type flip-flops and gating sections.
The shift register disclosed in this publication is usable in a scan signal line driving circuit or data signal line driving circuit of an active-matrix device. In the scan signal line driving circuit, the shift register is used to successively generate scan signals for the respective scan lines at predetermined timings. In the data signal line driving circuit, the shift register is used to generate a sampling signal for sending data signals to the respective source lines at predetermined timings. The data signals are supplied through data supply lines.
The timing charts of FIGS. 19, 21, and 23 do not take into account signal delays. As such, in the flip-flop of each stage, the rise of the output signal OUT (or output Q) and the fall of the control signal CK occur substantially at the same time, and the fall of the output signal OUT (or output Q) and the fall of the reset signal RB occur substantially at the same time. However, in actual flip-flops, there is a delay when the output signal OUT rises or falls in response to the fall of the control signal CK or reset signal RB.
For example, when a conventional shift register is used in the data signal line driving circuit, a signal delay in the output of the shift register causes the following problems. In the data signal line driving circuit, a sampling signal generated by the shift register needs to be timed with the data signal fed through the data feed lines. However, when a delay in the sampling signal shifts the generated timings of the sampling signal and the data signal fed through the data feed lines, desired data may not be properly sent to the source lines.
The problem of signal delay can also be caused when a conventional shift register is used in the scan signal line driving circuit, because the scan signal generated by the shift register needs to be timed with the data signals supplied to the source lines.
The foregoing problems can be solved by adjusting the respective timings of various input signals in expectation of a signal delay in the shift register. However, a problem of such a method is that it requires a means to adjust timings and thereby increases circuit size. Further, in order to provide enough margin for adjusting timings of input signals, the frequency of the master clock needs to be increased. This increases power consumption of the circuit.
A signal delay can be reduced by improving rising and falling characteristics of the shift register. However, this is associated with the following problems.
As an example, the following considers output signal Q2. In order to reduce a time delay in the fall of the output signal Q2, a reset signal (signal GB4) needs to be supplied to the reset terminal of FF2 without a delay. In addition, the falling characteristics of FF2 itself needs to be improved.
For example, in the operation of the FF3 (may have a structure shown in FIG. 18 or FIG. 20) that outputs an output signal Q3 used to generate signal GB4, the output speed of the output signal Q3 (rising characteristics of the output signal Q3) can be improved by improving the capability of Mn4. This can be achieved by designing Mp4 such that its W size (channel width) is smaller than that of Mn4. This enables a current to flow through Mn4 more easily and thereby reduces the rise time of the output Q.
Meanwhile, the output signal Q2 of FF2 is inverted to a signal GB3 and becomes the reset signal for the FF1 of the preceding stage. Again, in order to reduce a time delay in the fall of the output signal Q1, it is required to improve the rising characteristics of the output signal Q2 in FF2 for the reasons described above. (This is achieved by designing Mp4 such that its W size (channel width) is smaller than that of Mn4, thus improving the current flowing capability of Mn4.) However, in terms of reducing a time delay also in the fall of the output signal Q2, improving rising characteristics of the output signal Q2 defeats the idea of improving falling characteristics of the FF2 itself.
That is, a shift register using conventional flip-flops has a self-contained problem in that the falling characteristics of the output stage producing a signal that falls in response to a reset signal supplied from the next stage are sacrificed by the improved rising characteristics of its output signal OUT produced to improve resetting capability of the preceding stage.